1. Field of the Invention
The present invention relates to a method for producing semiconductor devices. More particularly, it relates to a method for producing bipolar transistors in an integrated circuit.
2. Description of the Prior Art
Recently, there have been attempts to make an integrated circuit (IC) comprising bipolar transistors, i.e., a bipolar IC, denser. When a base region and an emitter region of each of the bipolar transistors are decreased to increase the density, the accuracy of alignment of the emitter region in relation to the base region may become a problem. In a case where openings for a base electrode, an emitter electrode, and a collector electrode are simultaneously formed in an insulating layer, if the position of the openings for the electrodes is shifted from a predetermined position, a short-circuit between the emitter and collector or a decrease of the breakdown voltage between the emitter and collector, may occur.
A conventional method of producing a bipolar transistor is explained and the above-mentioned disadvantages are explained with reference to FIGS. 1 through 6.
On a P-type single crystalline silicon (Si) substrate (i.e., a P-type silicon wafer) 1 an N-type silicon epitaxial layer 2 is grown, as illustrated in FIG. 1. An N.sup.+ -type buried layer 3 (FIG. 1) for reducing the resistance of the collector is formed by a well-known process. An anti-oxidizing masking layer 4, e.g., a silicon nitride (Si.sub.3 N.sub.4) layer, having a thickness of, e.g., 100 nm is formed on the epitaxial layer 2 and is selectively removed by a photoetching process to leave portions corresponding to an isolation-providing region, a collector-providing region, and a base-providing region.
The epitaxial layer 2 is selectively thermally oxidized by using the silicon nitride layer 4 as a mask so that a relatively thick silicon dioxide (SiO.sub.2) layer (i.e., a so-called field oxide layer or field insulating layer) 5 is formed, as illustrated in FIG. 2. P-type impurities (e.g., boron) are introduced into a portion of the epitaxial layer 2 by an ion-implantation process by using the field oxide layer 5 and a patterned photoresist layer (not shown) as a mask to form a P-type isolation region 6. N-type impurities (donor e.g., phosphorus (P)) are introduced into another portion of the epitaxial layer 2 by an ion-implantation process by using the field oxide layer 5 and another patterned photoresist layer (not shown) as another mask to form an N-type collector contact region 7. Then the semiconductor body is annealed so as to activate the isolation region 6 and the collector contact region 7.
The silicon nitride layer 4 is removed by etching to expose portions of the epitaxial layer 2. The exposed portions are thermally oxidized to form a relatively thin silicon dioxide layer 8 having a thickness of, e.g., 100 nm, as illustrated in FIG. 3. A photoresist layer 9 is coated, exposed, and developed to form an opening 10 above a base-providing region. P-type impurities (acceptor e.g., boron (B)) are introduced into the epitaxial layer 2 through the opening 10 and the silicon dioxide layer 8 by an ion-implantation process to form a base region 11.
After removal of the photoresist layer 9, a silicon oxide layer 12 is formed on the thick field oxide layer 5 and on the thin silicon dioxide layer 8 by a chemical vapor deposition (CVD) process, as illustrated in FIG. 4. The oxide layers 12 and 8 are selectively etched by a conventional photoetching process to form a collector electrode opening 13, an emitter electrode opening 14 and a base electrode opening 15, simultaneously.
A polycrystalline silicon layer 16 (FIG. 5) having a thickness of, e.g., 100 nm is formed on the silicon oxide layer 12 and exposed portions of the epitaxial layer 2 within the openings 13, 14, and 15, by a CVD process. After a patterned photoresist layer (not shown) having two openings corresponding to the openings 13 and 14 is formed, N-type impurities (e.g., arsenic (As)) are introduced into the collector contact region 7 and the base region 11 through the polycrystalline silicon layer 16 by an ion-implantaton process using the photoresist layer as a mask so that an N.sup.+ -type collec contact region 17 and an N.sup.+ -type emitter region 18 are formed, as illustrated in FIG. 5. An annealing treatment is carried out and then a conductive layer, such as an aluminum (Al) layer, is formed on the exposed surface of the polycrystalline silicon layer 16 by vacuum evaporation. The aluminum layer is selectively etched by a conventional photoetching process to form a collector electrode 19, an emitter electrode 20, a base electrode 21, and conductive lines (not shown). The portion of the polycrystalline silicon layer 16 which is not covered with the electrodes 19, 20, and 21 and the conductive lines, is etched with a suitable etchant. Thus, the bipolar transistor shown in FIG. 5 is produced.
When the silicon oxide layers 12 and 8 are selectively etched to form the openings 13, 14, and 15 for the collector electrode 19, the emitter electrode 20, and the base electrode 21, respectively, in the above-mentioned production process, there is the possibility of shifting the position of the openings 13, 14, and 15 from the predetermined position. In this case, if the emitter electrode opening 14 is shifted to etch a portion of the thick field oxide layer 5, as illustrated in FIG. 6, the emitter region 18 is formed at the end portion of the base region 11, whereby a short-circuit 22 between the collector and emitter is formed. In a case where the degree of shift of the position of the openings is less than that of the degree of shift shown in FIG. 6, and if the end of the emitter region is very close to the end of the base region, the breakdown voltage between the emitter and collector is decreased. In order to prevent the above-mentioned disadvantages from occurring, it is possible to make the base region large. However, an enlarged base region hinders an increase of the density of the bipolar IC.